1. Field of the Invention
The present invention relates to a system for connecting one data processor such as a host computer with another data processor such as an extension sub-unit containing an I/O processor through a communication circuit such as an optical cable circuit and particularly to a data communication format usable in such a data communication system, a receiving side communication control depending on such a format and DMA transfer of data to the internal buffer means in the communication control system.
2. Description of the Related Art
In general, for data communication between two data processors, a DMA controller is provided in each of the transmission and receiving sides. Prior to transmission, the data processor on the transmission side first sets a source address, destination address, a data size and others. After the setting, the DMA controller is initiated to transmit data in a continuous manner.
On the other hand, the communication control unit on the receiving side includes a dedicated register for storing a start address, a data size and others necessary in the reception in addition to the DMA controller. Prior to reception, the dedicated register on the receiving side first sets the start address, data size and others. After the setting, the receiving side informs the transmission side that it is ready for reception and then initiates the DMA controller. After such a given procedure, the receiving side can actually receive data which are continuously sent from the transmission side.
The data thus received is always stored in a unique receive-only buffer in the communication control system on the receiving side.
Such a prior art system is effective for communication of a great volume of data, but unsuitable for transmission and reception of a small quantity of data since there is time required to perform the given procedure prior to the transmitting or receiving.
Since the received data is always stored in the unique receive-only buffer, information to be written in the other memory must be re-written in that memory after it has been once stored in the receive-only buffer. This requires unnecessary time and also another software for processing this procedure, the software being executed by the CPU in the communication control system.
DMA transfer generally utilizes two exclusive registers, that is, an address counter and a size counter. Prior to transfer, the start address and data size are set in the address and size counters, respectively. After the setting, a DMA controller will be started.
After having started, the DMA controller provides clock signals sequentially to the address and size counters and at the same time gives a read or write signal to the memory. Thus, the address counter will count up to specify the successive addresses in the memory sequentially. Data will be written into each of the specified addresses. On the other hand, the size counter counts down and generates an end signal when the contents in the size counter reache zero. When the end signal is received by the DMA controller, the latter terminates the DMA transfer.
However, such a DMA transfer technique requires two separate counters for address and data size. This increases the number of parts and renders the pre-transfer procedure complicated with more time required in the processing.